The invention relates to an integrated circuit with a memory, comprising a matrix of memory cells and sense amplifiers which are coupled thereto and outputs of which are connected to one another and to a common data bus.
A circuit of the kind set forth is known from IEEE Transactions on Electron Devices, Vol. ED-31, No. 9, September 1984: Masayuki et al., "Design of GaAs 1 kBit Static Ram", notably from FIG. 1. The switching speed of the sense amplifiers used in the circuit is inter alia dependent on the parasitic capacitive load formed by the common read lines (read bus). This capacitive load is generally proportional to the length of these lines and hence dependent on the number of memory columns to be coupled. In a memory design where the number of parallel-arranged memory columns may be specified, for example by a customer (for example, in the case of application specific integrated circuits (ASIC's)), either the access time for reading a memory cell will be dependent on the number of columns or the dimensions of the transistors in the sense amplifiers must be adapted in view of the above capacitive load when the desired number of parallel memory columns is changed, so that a new design is required for a part of the memory circuit. The repeated redimensioning of transistors requires additional design time and hence has a cost-increasing effect.